The third generation mobile radio system specifies convolutional codes and turbo-codes as channel coding techniques [3GPP, Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD); (3G TS 25.212 version 3.5.0(2000-12)), Release 1999].
In turbo-code encoders forward error correction is enabled by introducing parity bits. For turbo-codes, the original information, denoted as systematic information, is transmitted together with the parity information. The encoder for 3GPP includes two recursive systematic convolutional (RSC) encoders with constraint length K=4, which can also be interpreted as 8-state finite state machines. The first RSC encoder works on the block of information in its original sequence, and the second one works on the block of information in an interleaved sequence.
On the receiver side, there is a corresponding component decoder for each of them. Each component decoder implements a maximum-a-posteriori (MAP) algorithm, and is usually called a soft-in-soft-out (SISO) decoder.
Each block is decoded in an iterative manner. The systematic information and the parity information serve as inputs of the first component decoder (MAP1). The soft-output of MAP1 reflects its confidence on the received bits of being sent either as ‘0’ or ‘1’. These confidences are interleaved in the same manner as in the encoder, and are passed to the second component decoder (MAP2) as a-priori information. The second component decoder uses this information to bias its estimation comprising the interleaved systematic information and the parity information of the second encoder. The soft-outputs are again passed on to MAP1, and so on. The exchange continues until a stop criteria is fulfilled. Stop criteria range from simple cases, such as a “fixed number of iterations”, over cyclic redundancy check (CRC) to rather complex statistical analysis.
Implementation issues for turbo-decoder architectures using the MAP algorithm have already been discussed in several papers and are well known [A. Worm, Implementation Issues of Turbo-Decoders. Phd thesis, Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern, Forschungsberichte Mikroelektronik, Bd.3, Germany, 2001].
The MAP algorithm is transformed into the logarithmic domain to reduce operator strength [S. S. Pietrobond and A. S. Barbulescu, A Simplification of the Modified Bahl Decoding Algorithm for Systematic Convolutional Codes, In Proc. International Symposium on Information Theory and its Applications, pages 1073–1077, Sydney, Australia, November 1994]. Multiplications become additions and additions are replaced by a modified comparison. It includes a forward recursion, a backward recursion and soft-output calculation. To calculate a recursion step for a state, a modified accumulate-compare-select (ACS*) unit is necessary.
During turbo decoding only one MAP is active at a time. Due to the moderate throughput requirements both MAP calculations of the iterative loop can be mapped on a single hardware unit, thus only one MAP unit is necessary. In addition to the MAP unit, memories are needed to store the input and output values. Further storage is required for intermediate values like the a-priori information and the alpha-state-metrics. The interleaver and deinterleaver pattern generators also revert to memories. It becomes obvious, that for large block sizes memory dominates a turbo decoder architecture.
The size of the input RAMs for the systematic and parity information and the output RAM is determined by the block sizes which are defined in the 3GPP standard. The output RAM serves also as storage for the a-priori values. One soft-output memory is sufficient because the calculated soft-outputs are always written to the previous read position of the a-priori information. Thus no RAM is needed for the interleaved soft-outputs.
The size of the alpha-memory (which stores the alpha-states-metrics) can be reduced by introducing a windowing technique, where a window slides in the direction of increasing bit positions [H. Dawid and H. Meyr, Real-Time Algorithms and VLSI Architectures for Soft Output MAP Convolutional Decoding, In Proc. 1995 International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC'95), pages 193–197, Toronto, Canada, September 1995] for delivering almost the same communication performance as the original MAP decoder. The size of a window is significantly smaller than the block size. It ranges typically between 32 and 128. Windowing implicates additional computations during the acquisition. The saving in the alpha-memory, however, requires these extra computations.
In convolutional encoders forward error correction is also enabled by introducing parity bits. In 3GPP two different encoders with a constraint length K=9 are specified. Convolutional decoding, in contrast to turbo decoding, is non-iterative. The MAP algorithm is activated only once for each block. Although the interleaver is not needed and the block size is much smaller than for turbo-codes, the architecture of a 3GPP convolutional decoder is also dominated by memory. The I/O memories are rather small compared to the turbo decoder. The alpha-memory, however, exceeds that of the turbo decoder by a factor of 32 assuming the same window size. This is formed in the large number of states (256) of the convolutional decoder.
The main problem of the above mentioned turbo-code and convolutional code decoders is the need for large memories. Therefore, an implementation of individual decoders is costly.